High voltage silicon carbide (SiC) devices can be capable of handling high voltages, and may handle as much as about 100 amps or more of current, depending on the size of their active area. High voltage SiC devices have a number of important applications, particularly in the field of power conditioning, distribution and control.
A conventional power device structure has an n-type SiC substrate on which an n− epitaxial layer, which functions as a drift region, is formed. The device typically includes a P—N and/or Schottky junction on the n− layer, which acts as a main junction for blocking voltage in the reverse bias direction and providing current flow in the forward bias direction. A p-type junction termination extension (JTE) region, which is typically formed by ion implantation, may surround the main junction. The implants used to form the JTE region may be aluminum, boron, or any other suitable p-type dopant. The purpose of the JTE region is to reduce or prevent the electric field crowding at the edges, and to reduce or prevent the depletion region from interacting with the surface of the device. Surface effects may cause the depletion region to spread unevenly, which may adversely affect the breakdown voltage of the device. Other termination techniques include guard rings and floating field rings that may be more strongly influenced by surface effects. A channel stop region may also be formed by implantation of n-type dopants, such as nitrogen or phosphorus, in order to prevent/reduce extension of the depletion region to the edge of the device.
Additional conventional terminations of SiC Schottky diodes are described in “Planar Terminations in 4H—SiC Schottky Diodes With Low Leakage And High Yields” by Singh et al., ISPSD '97, pp. 157-160. A p-type epitaxy guard ring termination for a SiC Schottky Barrier Diode is described in “The Guard-Ring Termination for High-Voltage SiC Schottky Barrier Diodes” by Ueno et al., IEEE Electron Device Letters, Vol. 16, No. 7, July, 1995, pp. 331-332. Additionally, other termination techniques are described in published PCT Application No. WO 97/08754 entitled “SiC Semiconductor Device Comprising A PN Junction With A Voltage Absorbing Edge.”
In addition to junction termination extension (JTE), multiple floating guard rings (MFGR) and field plates (FP) are commonly used termination schemes in high voltage silicon carbide devices. Another conventional edge termination technique is a mesa edge termination.
Field plate termination is also a conventional technique for edge termination of a device and may be cost-effective. In conventional field plate devices, high fields are supported by the oxide layer under the metal field plate. This technique performs well for silicon devices where the highest field in the semiconductor is relatively low. However, in SiC devices the electric fields in the blocking state may be very high (˜2 MV/cm) which multiplies by a factor of 2.5 at the oxide-semiconductor interface. This leads to very high oxide fields and may result in long-term reliability problems. Thus, field plate terminations may be unsuitable for use in SiC devices.
The use of multiple floating guard rings in addition to JTE has been proposed as a technique for reducing the sensitivity of the JTE to implant dose variation. See Kinoshita et al., “Guard Ring Assisted RESURF: A New Termination Structure Providing Stable and High Breakdown Voltage for SiC Power Devices,” Tech. Digest of ISPSD '02, pp. 253-256. Kinoshita et al. reported that such techniques reduced the sensitivity to implant dose variation. However, the area utilized for termination was increased to almost three times the area of JTE alone as the guard rings are added to both the inner edge of the JTE and the outside of the JTE.
A conventional JTE-terminated PIN diode is illustrated in FIG. 1. As shown therein, a PIN diode 100 includes an n− drift layer 112 between a p+ layer 116 and an n+ substrate 114. FIG. 1 illustrates one half of a PIN-structure; the structure may include mirror image portions (not shown). An anode contact 123 is on the p+ layer 116, and a cathode contact 125 is on the n+ substrate 114. A junction termination extension (JTE) region 120 including a plurality of JTE zones 120A, 120B, 120C is provided in the n− drift layer 112 adjacent the p+ layer 116. The JTE zones 120A, 120B, 120C are p-type regions that may have levels of charge that decrease outwardly in a stepwise fashion with distance from the PN junction between the p+ layer 116 and the n− drift layer 112. Although three JTE zones 120A, 120B, 120C are illustrated, more or fewer JTE zones may be provided.
The JTE zones 120A, 120B, 120C may be formed by successive implantation of ions into the n− drift layer 112. However, such implantation may require multiple mask and implantation steps, increasing the complexity and expense of production. This may be exacerbated as the number of JTE zones is increased. Furthermore, the stepwise doping gradient provided by such an approach may not provide an ideal termination.